The present invention relates to a semiconductor memory device and, more particularly, to the layout of an SRAM (Static Random Access Memory) cell having a CMOS structure.
An SRAM having a CMOS structure is widely used as a memory device integrated in a logical IC. As a memory element constituting the memory device, the most basic one is a 1-port memory cell (SRAM cell) shown in FIG. 16, which is constituted by six transistors.
A P-channel MOS transistor P1 and an N-channel MOS transistor N1 constitute an inverter IN2 in FIG. 17 showing an equivalent circuit, whereas a P-channel MOS transistor P2 and an N-channel MOS transistor N2 constitute an inverter IN1. The inverters IN1 and IN2 have a relationship in which their input and output terminals are cross-connected to each other. The output terminal of the inverter IN1 and the input terminal of the inverter IN2 are connected to a bit line BL via a transfer gate transistor N3. The input terminal of the inverter IN1 and the output terminal of the inverter IN2 are connected to a bit line /BL via a transfer gate transistor N4. The gates of the transistors N3 and N4 are connected to a word line WL.
This 6-transistor memory cell has a layout like the one shown in FIGS. 10 and 11 showing the layout of a device associated with the present invention. FIG. 10 shows an underlying layer including a diffusion layer formed on a substrate surface to constitute a transistor, a polysilicon wiring layer formed on the upper surface of the diffusion layer, and a first metal wiring layer 1 formed on the upper surface of the polysilicon wiring layer. FIG. 11 shows an overlying layer including second and third metal wiring layers 2 and 3 formed on the upper surface of the underlying layer. FIG. 12(a) shows the marks of a contact and a via hole used in FIGS. 10 and 11; FIG. 12(b), those of the diffusion layer, the polysilicon film, and the metal wiring layer 1; and FIG. 12(c), those of the metal wiring layers 2 and 3.
A boundary BL11 between an N-well region where the P-channel MOS transistors P1 and P2 shown in FIG. 10 are formed, and a P-well region where the N-channel MOS transistors N1 to N4 are formed is present parallel to the word line WL shown in FIG. 11. At an upper portion with respect to the line A--A parallel to the boundary BL11, a polysilicon wiring layer PL11 connected to the gate of the transistor P1 and a polysilicon wiring layer PL12 connected to the gate of the transistor P2 are laid out translationally symmetrical to each other.
At a lower portion with respect to the line A--A, a diffusion layer DR11 constituting the transistors N1 and N3 and a diffusion layer DR12 constituting the transistors N2 and N4 are laid out mirror-symmetrical about the y-axis perpendicular to the word line WL.
As is apparent from FIG. 10, in this layout, the ground line GND and the word line WL are formed of the metal wiring layers 3, the bit lines BL and /BL are formed of the metal wiring layers 2, and all the remaining portions are made of the polysilicon wiring layers PL11 and PL12 and the metal wiring layer 1. The metal wiring layer 3 is functionally unnecessary because the word line WL made of the polysilicon wiring layers PL11 and PL12 is connected across the memory cell to a word line WL of another adjacent memory cell. The ground line GND can be made of the metal wiring layer 2 to be parallel to the bit lines BL and /BL. Therefore, the layout shown in FIGS. 10 and 11 can be constituted by the polysilicon wiring layers PL11 and PL12 and the metal wiring layers 1 and 2.
This layout is constituted with the minimum area so as to make the design standards (design rule) limited by process techniques satisfy the following conditions.
(a1) The number of metal wiring layers is limited to one or two.
(a2) The design rules of the minimum line width and minimum interval of the metal wiring layer are larger (about two times) than those of the polysilicon layer.
(a3) A contact hole serving as an opening portion between the diffusion layer or the polysilicon wiring layer and the metal wiring layer 1, and the first through hole or first via hole serving as an opening portion between the metal wiring layers 1 and 2 do not directly vertically overlap each other. Since the area of the contact hole is as large as about two times the minimum line width of a normal metal wiring layer, many contact holes or through holes are not formed within the cell to prevent an increase in cell area.
(a4) The boundary between the N- and P-well regions is present between the P-channel MOS transistor and the N-channel MOS transistor. These well regions having different conductivity types are isolated by element isolation using LOCOS. Therefore, the isolation width between the P- and N-well regions must be set much larger (about four times) than the element isolation width between well regions having the same conductivity type.
To satisfy the above conditions, a wiring layer is made of a polysilicon film as much as possible, and a wasteful region must be effectively utilized such that complicated wiring cross connection is performed in the isolation region between the P- and N-well regions.
However, with the recent advance in process techniques, the design rule is changing as follows.
Along with practical use of chemical mechanical polishing (CMP), a technique of planarizing a metal wiring layer advances.
(b1) Even if the number of metal wiring layers increases to three or four, the yield does not greatly decrease.
(b2) The design rules of the minimum line width and minimum interval of the metal wiring layer are almost equal to those of the polysilicon layer.
(c2) A borderless contact technique is introduced, and the contact portion can be formed by the same design rule in which its area is equal to the minimum line width of the metal wiring layer. Further, a stacked-via structure in which a contact hole and a through hole are formed to directly vertically overlap each other can be realized.
In addition, element isolation advances from LOCOS to trench isolation (ST1).
(c1) The isolation width between the P- and N-well regions is almost equal to the element isolation width between well regions having the same conductivity type (P-well regions or N-well regions).
Owing to the advance in process techniques, a layout like the one shown in FIGS. 10 and 11 is not optimal. For example, the polysilicon wiring layers PL11 and PL12 are laid out translationally symmetrical to each other with a T shape, resulting in a large wasteful region. Since the N-channel MOS transistors N1 and N3 are laid out to be perpendicular to each other, the diffusion layer is bent in an L shape, and the cell area is wasted.
FIGS. 13 and 14 show an improvement of the layout shown in FIGS. 10 and 11. The basic layout and geometrical shapes of the transistors N1 to N4 and P1 and P2 are the same as those in FIGS. 10 and 11 except that the metal wiring layer 2 replaces the polysilicon wiring layers PL11 and PL12 cross-connected in the layout shown in FIGS. 10 and 11, and along with this change, the metal wiring layer 3 constitutes the bit lines BL and /BL and the ground line GND. With the layout shown in FIGS. 13 and 14, the cell area decreases by about 10%, compared to the one shown in FIGS. 10 and 11.
Also in the layout shown in FIGS. 13 and 14, however, the diffusion layers respectively constituting the transistors N1 and N3 and the transistors N2 and N4 are inevitably formed into an L shape, wasting the cell area.
As described above, the layout of the SRAM cells shown in FIGS. 10 to 15 suffers the problems in which the geometrical shape such as the L shape of the diffusion layer is wasteful, and the element area is large.